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IronMan: exploring the power of GNN and RL in EDA

This project explores the power of graph neural network (GNN) and reinforcement learning (RL) in the EDA area: high-level synthesis, specifically. GPP is a highly accurate graph-neural network-based performance and resource predictor; RLMD is a reinforcement-learning-based multi-objective DSE engine for resource allocation; CT is a code transformer that extracts the data flow graph from original HLS C/C++ and generates synthesizable code with new HLS directives.

  • [Ongoing] Initial results can be found in this paper.

  • [Ongoing] We're exploring the power of GNNs in broader applications in EDA -- accuracy prediction for approximate computing, circuit quality prediction, etc.

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NAIS: Neural Architecture and Implementation Search

This project focuses on a novel co-search methodology beyond NAS (neural architecture search), called NAIS - neural architecture and implementation search. NAIS incorporates hardware implementation search into NAS to produce hardware-efficient AI algorithms as well as optimized hardware implementations, within limited hardware resource and performance constraints.

  • [Publications] DAC'19, ICCAD'19, DAC'20

  • [Ongoing] We are exploring NAIS for multi-modal multi-task (MMMT) neural networks targeting heterogeneous platforms

Graph-based Computation Acceleration

This project focuses on sw/hw co-design for graph-based computation and processing, such as graph neural network and graph algorithms (pagerank, recommender system, etc.), for acceleration, memory reduction, or energy reduction.

  • [Publications] DAC'21 (coming soon)

  • [Ongoing] We are exploring more optimization opportunities of acceleration and memory reduction through both algorithm and dedicated hardware architecture.

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HLS: High-Level Synthesis assisting hardware design

High-Level Synthesis (HLS) is an automated design process that interprets an algorithmic description (C, C++, SystemC, etc.) of the desired behavior and creates digital hardware (VHDL, Verilog, etc.) that implements that behavior [ref]. HLS greatly boosts productivity for hardware development such as ASIC and FPGA design.

Our main research interests include:​

  • [past] Traditional HLS: core algorithms such as operation scheduling, functional unit and register binding.

  • [current] Modern HLS: domain-specific (machine learning, graph processing) HLS, HLS for heterogeneous platforms, etc.

  • [current] HLS design space exploration: to further alleviate human efforts

  • [future] HLS for agile development!

FPGA Acceleration for DNNs

We have proposed three levels of key techniques for FPGA acceleration for DNNs, including:

  • Bit-level: low-loss low-bit data quantization techniques.

  • Module-level: high efficiency computing unit, i.e., IP cores on FPGA. Such IPs are open-sourced and are written in C, which can be synthesized using HLS tools.

  • Architecture-level: a fine-grained, tile-based low-latency FPGA accelerator.

ML algorithm and system for autonomous driving

We proposed a hybrid GPU + FPGA platform for autonomous driving cars, which introduces redundancy into system for reliability: the FPGA system acts as a fallback system when GPU failure occurs. In addition, hardware heterogeneity decouples the development of the main driving task and safe-mode driving task, as well as the development of GPU and FPGA algorithms.

We're also working on 2D/3D object detection for autonomous driving ith/without lidar sensors.