2021

C [ASAP]

Xinheng Liu, Yao Chen, Cong Hao, Ashutosh Dhar, Deming Chen

WinoCNN: Kernel Sharing Winograd Systolic Array for Efficient ConvolutionalNeural Network Acceleration on FPGAs

IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2021

C [GLSVLSI]

Yao ChenCole HawkinsKaiqi ZhangZheng ZhangCong Hao

3U-EdgeAI: Ultra-Low Memory Training, Ultra-Low BitwidthQuantization, and Ultra-Low Latency Acceleration

ACM Great Lakes Symposium on VLSI (GLSVLSI), 2021 (Invited).

[paper]

C [GLSVLSI]

Nan Wu, Yuan Xie, Cong Hao

IronMan: GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learning

ACM Great Lakes Symposium on VLSI (GLSVLSI), 2021, Best Paper Award

[paper]

C [AICAS]

Cong Hao, Deming Chen

Software/Hardware Co-design for Multi-modal Multi-task Learning in Autonomous System

IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2021 (Invited).

[paper]

J [D&T]

Cong Hao, Jordan Dotzel, Jinjun Xiong, Luca Benini, Zhiru Zhang, Deming Chen

Enabling Design Methodologies and Future Trends forEdge AI: Specialization and Co-design

IEEE Design & Test, 2021

[paper] [citation]

C [DAC]

Lixiang Li, Yao Chen, Zacharie Zirnheld, Pan Li, Cong Hao

MeLoPPR: Software/Hardware Co-design for Memory-efficient Low-latency Personalized PageRank

Proceedings of IEEE/ACM Design Automation Conference (DAC), 2021.

[code] [paper]

C [ICLR]

Kaiqi Zhang, Cole Hawkins, Xiyuan Zhang, Cong Hao, Zheng Zhang

On-FPGA training with ultra memory reduction: A low-precision tensor method

ICLR Workshop on Hardware-Aware Efficient Training (HAET), 2021.

[paper]

C [DATE]

​Dongning Ma, Rahul Thapa, Xingjian Wang, Cong Hao, Xun Jiao

Workload-Aware Approximate Computing Configuration

IEEE/ACM Design, Automation & Test in Europe Conference (DATE), 2021.

[paper]

2020

J [TC]

Cheng Gong, Ye Lu, Tao Li, Cong Hao, Deming Chen, Yao Chen

VecQ: High Accuracy DNN Model Compression with Vectorized Weight Quantization

IEEE Transactions of Computers, 2020

[paper] [code]

J [TCDS]

Jianwei Zheng, Chao Lu, Cong Hao, Deming Chen, Donghui Guo

Improving the Generalization Ability of Deep Neural Networks for Cross-Domain Visual Recognition

IEEE Transactions on Cognitive and Developmental Systems, 2020

C [GLSVLSI]

Cong Hao, Chen Yao, Xiaofan Zhang, Yuhong Li, Jinjun Xiong, Wen-mei Hwu, Deming Chen

Effective Algorithm-Accelerator Co-design for AI Solutions on Edge Devices

Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), 2020

C [DAC]

Yuhong Li*, Cong Hao*, Xiaofan Zhang, Chen Yao, Jinjun Xiong, Wen-mei Hwu, Deming Chen

EDD: Efficient Differentiable DNN Architecture and Implementation Co-search for Embedded AI Solutions

Proceedings of IEEE/ACM Design Automation Conference (DAC), 2020.​

C [FPGA]

Pengfei Xu, Xiaofan Zhang, Cong Hao, Yang Zhao, Zetong Guan, Yongan Zhang, Yue Wang, Deming Chen, Yingyan Lin

AutoDNNchip: An Automated DNN Chip Generator through Compilation, Optimization, and Exploration

Proceedings of ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), 2020.

C [MLSys]

Xiaofan Zhang, Haoming Lu, Cong Hao, Jiachen Li, Bowen Cheng, Yuhong Li, Kyle Rupnow, Jinjun Xiong, Thomas Huang, Honghui Shi, Wen-mei Hwu, Deming Chen

SkyNet: a Hardware-Efficient Method for Object Detection and Tracking on Embedded Systems

The Conference on Machine Learning and Systems (SysML), 2020.​

[paper] [code]

Journals

  1. [D&T'21] Cong Hao, Jordan Dotzel, Jinjun Xiong, Luca Benini, Zhiru Zhang, Deming Chen, "Enabling Design Methodologies and Future Trends forEdge AI: Specialization and Co-design", IEEE Design & Test, 2021

  2. [TC'20] Cheng Gong, Ye Lu, Tao Li, Cong Hao, Deming Chen, Yao Chen, "VecQ: High Accuracy DNN Model Compression with Vectorized Weight Quantization", IEEE Transactions of Computers, 2020

  3. [TCDS'20] Jianwei Zheng, Chao Lu, Cong Hao, Deming Chen, Donghui Guo, "Improving the Generalization Ability of Deep Neural Networks for Cross-Domain Visual Recognition", IEEE Transactions on Cognitive and Developmental Systems, 2020

  4. [TED'19] Zhao Yi, Cong Hao, and Takeshi Yoshimura. "Thermal and Wire length Optimization With TSV Assignment for 3D-IC", IEEE Transactions on Electron Devices, 2019

  5. Ma Jiayi, Cong Hao, and Kundong Wang. "Decomposing and Cluster Refinement Design Method for Application-Specific Network-on-Chips.", Journal of Shanghai Jiao Tong University (Science), 2018

  6. [IEICE'17] Cong Hao, Takeshi Yoshimura. "An Efficient Multi-Level Algorithm for 3D-IC TSV Assignment", IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences, March 2017

  7. [TCAD'17] Cong Hao, Nan Wang, and Takeshi Yoshimura. "A Unified Scheduling Approach for Power and Resource Optimization with Multiple V-dd or/and V-th in High-Level Synthesis", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, January 2017.

  8. [TVLSI'16] Cong Hao, Jianmo Ni, Nan Wang, and Takeshi Yoshimura. "Interconnection Allocation between Functional Units and Registers in High-Level Synthesis", IEEE Transactions on Very Large Scale Integration Systems, September 2016.

  9. [TVLSI'16] Wang Nan, Wei Zhong, Cong Hao, Song Chen, Takeshi Yoshimura, and Yu Zhu. "Leakage-power-aware scheduling with dual-threshold voltage design.", IEEE Transactions on Very Large Scale Integration Systems, September 2016.

  10. [IEICE'17] Nan Wang, Song Chen, Cong Hao, Haoran Zhang, and Takeshi Yoshimura. "Leakage Power-Aware Scheduling in High-Level Synthesis.", IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences, 2014.

2019

J [TED]

Zhao Yi, Cong Hao, and Takeshi Yoshimura

Thermal and Wire length Optimization With TSV Assignment for 3D-IC

IEEE Transactions on Electron Devices, 2019

C [ICCAD]

Cong Hao, Yao Chen, Xinheng Liu, Atif Sarwari, Daryl Sew, Ashutosh Dhar, Bryan Wu, Dongdong Fu, Jinjun Xiong, Wen-mei Hwu, Junli Gu, Deming Chen

NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous Driving

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2019.

C [DAC]

Cong Hao, Xiaofan Zhang, Yuhong Li, Sitao Huang, Jinjun Xiong, Kyle Rupnow, Wen-Mei Hwu, Deming Chen

FPGA/DNN Co-Design: An Efficient Design Methodology for IoT Intelligence on the Edge

Proceedings of IEEE/ACM Design Automation Conference (DAC), 2019.

C [SiPS]

Cong Hao, Atif Sarwari, Bryan Wu, Zhijie Jin, Junli Gu, Deming Chen

A Hybrid GPU + FPGA System Design for Autonomous Driving Cars

Proceedings of IEEE International Workshop on Signal Processing Systems (SiPS), 2019 (invited). 

C [ISVLSI]

Yao Chen, Kai Zhang, Cheng Gong, Cong Hao, Xiaofan Zhang, Tao Li, and Deming Chen

TDLA: An Open-source Deep Learning Accelerator for Ternarized DNN Models on Embedded FPGA

Proceedings of IEEE Computer Society Annual Symposium on VLSI, 2019.​

C [IJCNN]

Cheng Gong, Ye Lu,Cong Hao, Xiaofan Zhang, Tao Li, Deming Chen, and Yao Chen

μL2Q: An Ultra-Low Loss Quantization Method for DNN Compression

Proceedings of International Joint Conference on Neural Networks (IJCNN), 2019.

W [ICML]

Xiaofan Zhang, Cong Hao, Yuhong Li, Yao Chen, Jinjun Xiong, Wen-Mei Hwu, Deming Chen

A Bi-Directional Co-Design Approach to Enable Deep Learning on IoT Devices

Joint Workshop on On-Device Machine Learning Compact Deep Neural Network Representations, ICML Workshop, 2019, Best Poster Award

C [FPGA]

Yao Chen, Jiong He, Xiaofan Zhang, Cong Hao, and Deming Chen

Cloud-DNN: An Open Framework for Mapping DNN Models to Cloud FPGAs

Proceedings of ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), 2019.

Prior to 2019

J [SJTU]

Ma Jiayi, Cong Hao, Kundong Wang

Decomposing and Cluster Refinement Design Method for Application-Specific Network-on-Chips

Journal of Shanghai Jiao Tong University (Science), 2018

J [IEICE]

Cong Hao, Takeshi Yoshimura

An Efficient Multi-Level Algorithm for 3D-IC TSV Assignment

IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences, March 2017

J [TCAD]

Cong Hao, Nan Wang, and Takeshi Yoshimura

A Unified Scheduling Approach for Power and Resource Optimization with Multiple V-dd or/and V-th in High-Level Synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, January 2017.

J [TVLSI]

Cong Hao, Jianmo Ni, Nan Wang, Takeshi Yoshimura

Interconnection Allocation between Functional Units and Registers in High-Level Synthesis

IEEE Transactions on Very Large Scale Integration Systems, September 2016.

J [TVLSI]

Wang Nan, Wei Zhong, Cong Hao, Song Chen, Takeshi Yoshimura, Yu Zhu

Leakage-power-aware scheduling with dual-threshold voltage design

IEEE Transactions on Very Large Scale Integration Systems, September 2016.

J [IEICE]

Nan Wang, Song Chen, Cong Hao, Haoran Zhang, Takeshi Yoshimura

Leakage Power-Aware Scheduling in High-Level Synthesis

IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences, 2014.

C [ICSICT]

Cong Hao, Deming Chen

Deep Neural Network Model and FPGA Accelerator Co-design: Opportunities and Challenges

Proceedings of IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT),2018.

C [PATMOS]

Yi Zhao, Cong Hao, Takeshi Yoshimura

TSV Assignment of Thermal and Wire length Optimization for 3D-IC Routing

28th IEEE International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2018

C [CEEC]

Cong Hao, Takeshi Yoshimura

Application of on-line machine learning in optimization algorithms: A case study for local search

Computer Science and Electronic Engineering (CEEC), IEEE, 2017

C [MWSCAS]

Yangyizhou Wang, Cong Hao, Takeshi Yoshimura

A Particle Swarm Optimization and Branch and Bound BasedAlgorithm for Economical Smart Home Scheduling

In 20th IEEE MWSCAS, 2017

C [PATMOS]

Yuxin Qian, Cong Hao, Takeshi Yoshimura

3D-IC signal TSV assignment for thermal and wire length optimization

27th IEEE International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2017

C [ISOCC]

Jiayi Ma, Cong Hao, Takeshi Yoshimura

Power-efficient Partitioning and Cluster Generation Design for Application-Specific Network-on-Chip

In 13th IEEE ISOCC, 2016

C [MWSCAS]

Hui Zhu, Cong Hao, Takeshi Yoshimura

Thermal-Aware Floorplanning for NoC-Sprinting

In 59th IEEE MWSCAS,2016

C [MWSCAS]

Cong Hao, Takeshi Yoshimura

Economical Smart Home Scheduling for Single and Multiple Users

In 59th IEEE MWSCAS, 2016

C [NEWCAS]

Cong Hao, Nan Ding, Takeshi Yoshimura

An Efficient Algorithm for 3D-IC TSV Assignment

In 14th IEEE NEWCAS,2016, Best Student Paper

W [WAPCO]

Cong Hao, Takeshi Yoshimura

EACH: An Energy-Efficient High-Level Synthesis Framework for Approximate Computing

In 2nd IEEE WAPCO, 2016

C [ASICON]

Jian-Mo Ni, Qian Ai, Cong Hao, Takeshi Yoshimura, Nan Wang

Primal-Dual Method based Simultaneous Functional Unit and Register Binding

In 10th ASICON, 2015

W [IWLS]

Cong Hao, Nan Wang, Jian-Mo Ni, Takeshi Yoshimura

An Efficient Tabu Search Methodology for Port Assignment Problem in High-Level Synthesis

In 24th IWLS, 2015

C [ASICON]

Cong Hao, Jian-Mo Ni, Hui-Tong Wang, Takeshi Yoshimura

Simultaneous Scheduling and Binding For Resource Usage and Interconnect Complexity Reduction in High-Level Synthesis

In 11th IEEE ASICON, 2015, Best Student Paper

C [ASP-DAC]

Cong Hao, Song Chen, Takeshi Yoshimura

Network simplex method based Multiple Voltage Scheduling in Power-efficient High-level synthesis

In 18th IEEE ASP-DAC, 2013, IEICE VLD Excellent Student Award

C [ASICON]

Cong Hao, Nan Wang, Song Chen, Takeshi Yoshimura, Min-You Wu

Interconnection allocation between functional units and registers in High-Level Synthesis

In 10th IEEE ASICON, 2013, Best Student Paper

C [ASICON]

Wang Nan, Cong Hao, Nan Liu, Haoran Zhang, Takeshi Yoshimura

Timing and resource-constrained leakage power-aware scheduling in high-level synthesis

In 10th IEEE ASICON, 2013,

C [ASQED]

Cong Hao, Haoran Zhang, Song Chen, Takeshi Yoshimura, Min-You Wu

Port assignment for multiplexer and interconnection optimization

In 5th IEEE ASQED, 2013

C [ASICON]

Haoran Zhang, Cong Hao, Nan Wang, Song Chen, Takeshi Yoshimura

Power and resource-aware scheduling with multiple voltages

In 10th IEEE ASICON, 2013, Best Student Paper

C [VLSI-DAT]

Cong Hao, Song Chen, Takeshi Yoshimura

Port assignment for interconnect reduction in high-level synthesis

In 19th IEEE VLSI-DAT, 2012, Best Paper Nomination